The invention relates to booting from a non-XIP memory, and more particularly, to booting from a non-XIP memory utilizing a boot engine that does not utilize ECC capabilities when booting.
Modern communications technology utilizes both NOR flash memory and NAND flash memory. NOR flash memory is an XIP (Execution in Place) memory that supports booting, and allows code to be directly executed. The disadvantage of NOR flash memory, however, is that the density is limited. For storing images and content, particularly in high-end communication devices, NAND flash memory is the preferred option. The advantages of NAND flash memory over NOR flash memory are faster program and write speeds, and a higher density. NAND flash memory is a non-XIP memory, and therefore has to shadow codes to an XIP memory (e.g. a RAM) before booting can take place. Non-XIP memories often suffer from bit-flipping, where a bit is reversed or reported as reversed. Bit-flipping can have serious consequences for a CPU. When booting from a non-XIP memory, therefore, the system will carry out EDC and ECC checks during the code shadowing process.
Booting from a non-XIP memory can be entirely hardware based or a combination of hardware and software. The hardware method is called a boot engine method. The CPU operation is paused by the boot engine through well-known techniques such as gating a clock fed into the CPU or asserting a reset signal to the CPU, and a boot loader code, contained in the non-XIP memory, is shadowed to the XIP memory. The boot loader code is then executed by the boot engine, so Operation System (OS) images stored in the non-XIP memory can be shadowed to the XIP memory. EDC and ECC checks are carried out at the same time. Code shadowing, EDC, and ECC processes are performed by the boot engine. After all the codes have been shadowed to the XIP memory, the boot engine re-activates the CPU, which then executes the OS images in the XIP memory. In short, the related art boot engine method utilizes a boot engine, an individual hardware component different from the existing CPU, to handle all booting sequences including hardware initialization, code shadowing, EDC/ECC checking, and OS start-up.
The software method utilizes a ROM that contains the boot loader code. The ROM is mapped at the top of the CPU address space, and also contains a Reset Code. The Reset Code, executed by the CPU, initializes the hardware, and the boot loader code in the ROM is then executed by the CPU. The boot loader code is for shadowing the OS images in the non-XIP memory to the XIP memory. Similar to the functionality of the above boot engine, the boot loader code is further executed to perform EDC and ECC checks at the same time. Once all the images have been shadowed, the CPU will execute the OS images in the XIP memory. In short, the related art software method utilizes a CPU to handle all booting sequences including hardware initialization, code shadowing, EDC/ECC checking, and OS start-up.
The related art software method needs a longer period of time to complete the booting sequence, but is easier to implement. The related art hardware method requires a shorter period of time to complete the booting sequence, but has greater architectural complexity due to the complicated EDC/ECC hardware. It is desired to invent a new and improved booting system having reduced architectural complexity and requiring a shorter period of time to complete the booting sequence.